1. Field of the Invention
The present invention relates to a central processing unit (CPU) including a two-valued (or binary)/n-valued conversion unit and to an electronic computer apparatus having the central processing unit.
2. Description of the Related Art
As is well known, a CPU performs operations on data as a specified group of binary digits, or bits, known as a word. The word size (or bit length) of the CPU is becoming progressively longer with improving performance of the CPU. Therefore, the number of signal lines constituting a data bus or an address bus, e.g. hence the bus width, is becoming increasingly wide. The conventional standard 32-bit CPU requires a 32-line parallel bus. However, a narrower bus width of the CPU is desirable for the advancing size reduction and the higher reliability of the CPU.
Conventionally, the only method of reducing the bus width has been to use a time-sharing system. However, this time-sharing system has a disadvantage that the signal transmission speed that is, the bus speed is slow. This disadvantage is very serious because the bus speed of the CPU determines the performance, such as a high-speed operability of the computer system.